PROCESS × DEVICE · HYBRID R&D ENGINEER

The person who knows both
CVD thin-film process and CMOS devices

11 years on the semiconductor front line — from 3D NAND to logic devices, from TFT to thin-film process windows. A cross-disciplinary process-device background that translates process problems into device language.

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About

About me

I'm Diamond, a hybrid semiconductor R&D engineer. Over the past 11 years I've served at leading domestic memory and specialty-process fabs — working on CVD thin-film process and device R&D for 3D NAND, as well as TFT device development. Today I focus on CVD process development and process-device co-optimization.

My edge is this: I can tune thin-film uniformity, step coverage and stress at the chamber level, and at the device level map those film parameters into I-V characteristics and yield. This process-to-device perspective is especially rare in Process Integration Engineering (PIE) and Yield Enhancement (YE) roles.

I'm currently a PhD candidate, turning hands-on fab experience into reusable methodology — which is what this site is for.

11yrssemiconductor R&D
60+patents (5 granted)
3tier-1 fab stints
PhDIC Engineering, in progress
Capabilities

Core skills

Process and device driven in parallel — not one as an extension of the other, but the true intersection of both.

◈ CVD Thin-Film Process

From chamber process-window development to mass-production yield ramp — covering film thickness uniformity, step coverage, stress control and defect suppression.

Uniformity / step coverage / stress
Process-window dev. & SPC
Defect suppression & yield

⊞ CMOS / Device R&D

Spanning 3D NAND, logic devices and TFT — able to correlate thin-film process parameters into device electrical and reliability models.

3D NAND / logic / TFT devices
Process-device modeling
Electrical / reliability analysis
Services

What I can help with

Turning front-line experience into deliverables. All services are based on open-domain knowledge and methodology — no confidential information from any former employer is involved.

01

Résumé Optimization (Semiconductor)

Tailored to process / device / PIE / YE roles — restructure your résumé and quantify the impact so recruiters and interviewers see the highlights in 10 seconds.

View pricing →
02

Mock Interview (Device / PIE)

Role-play technical interviews based on real job descriptions — covering thin-film process, device physics, failure analysis and project deep-dives.

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03

Technical Consulting / Process Review

Part-time advisory for equipment vendors, material suppliers and startups on thin-film process windows and device-structure reviews.

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04

Process Training / Knowledge Sharing

Hands-on semiconductor thin-film process courses and public talks for new grads and career-switchers.

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Writing

Articles & thoughts

Turning the pitfalls and the "aha" moments from the fab into reusable methodology.

05failure modes
Semiconductor thin-film process · field checklist

5 Common CVD Thin-Film Failure Modes — A Field Checklist from an 11-Year Process Engineer

Poor uniformity, particle contamination, step-coverage voids, film stress cracking, and abnormal electrical/composition. Each with its symptom, mechanism and debugging path.

Read more →
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Coming soon

From 3D NAND to Logic Devices: A Process-Device Engineer's Perspective

Why people who span process-device are scarcer — and more valuable — in PIE / YE roles.

Stay tuned
Contact

Let's talk about your need

Career coaching, technical collaboration, content partnership — all welcome. Usually same-day reply on working days.

StatusPhD in progress · open to collaboration
PrincipleOpen-domain · compliant & confidential
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