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From 3D NAND to Logic Devices: A Process-Device Engineer's Perspective
Why people who span process-device are scarcer — and more valuable — in PIE / YE roles.
Stay tunedPROCESS × DEVICE · FRONT-LINE SEMICONDUCTOR PROCESS ENGINEER
From 55nm to 14nm, and 32- to 196-layer 3D NAND —
From 55nm to 14nm, and 32- to 196-layer 3D NAND —
all built hands-on
I'm Diamond. 11 years on the semiconductor production line — from 55nm down to 14nm logic, and from 32-layer to 196-layer 3D NAND, I took multiple product lines from zero to one and owned the full yield ramp-to-mass-production cycle. Not seen-it, done-it.
CVD thin-film (low-k / STI HARP / high-stress SiN) and CMOS devices — I've hit the wall on both. The hybrid process-device background lets me translate a process issue straight into device language to find root cause. 60+ patents and years of yield & failure triage notes are baked into the docs here.
Stuck on a process window that won't move, a resume that undersells you, or an interview "why" you can't nail? I can help turn that fuzzy instinct into an actionable plan and a story you can tell clearly.
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